- instructions per cycle
- Вычислительная техника: число команд, выполняемых за цикл
Универсальный англо-русский словарь. Академик.ру. 2011.
Универсальный англо-русский словарь. Академик.ру. 2011.
Instructions Per Cycle — In computer architecture, Instructions Per Clock (Instruction Per Cycle or IPC) is a term used to describe one aspect of a processor s performance: the average number of instructions executed for each clock cycle. It is the multiplicative inverse … Wikipedia
Instructions per cycle — Die Maßeinheit Instructions per Cycle (IPC) bezeichnet die Anzahl der von einem Prozessor in einem Taktzyklus ausführbaren Befehle. Es handelt sich in der Regel um einen Mittelwert, da die Anzahl der ausgeführten Befehle pro Taktzyklus bei den… … Deutsch Wikipedia
Instructions per second — (IPS) is a measure of a computer s processor speed. Many reported IPS values have represented peak execution rates on artificial instruction sequences with few branches, whereas realistic workloads typically lead to significantly lower IPS values … Wikipedia
Cycles Per Instruction — In computer architecture, Cycles per instruction (clock cycles per instruction or clocks per instruction or CPI) is a term used to describe one aspect of a processor s performance: the number of clock cycles that happen when an instruction is… … Wikipedia
Cycles per instruction — In computer architecture, cycles per instruction (aka clock cycles per instruction, clocks per instruction, or CPI) is a term used to describe one aspect of a processor s performance: the number of clock cycles that happen when an instruction is… … Wikipedia
Urban Cycle Polo — is a variation of standard Cycle polo where two teams ride bicycles and use mallets to score goals with a small ball. Urban cycle polo does not have as many rules as its predecessor and can be played in a variety of locations common to urban… … Wikipedia
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Central processing unit — CPU redirects here. For other uses, see CPU (disambiguation). An Intel 80486DX2 CPU from above An Intel 80486DX2 from below … Wikipedia
Parallel computing — Programming paradigms Agent oriented Automata based Component based Flow based Pipelined Concatenative Concurrent computing … Wikipedia
Classic RISC pipeline — In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000,… … Wikipedia
PA-8000 — HP PA 8000. The PA 8000 (PCX U), code named Onyx, is a microprocessor developed and fabricated by Hewlett Packard (HP) that implemented the PA RISC 2.0 instruction set architecture (ISA).[1] It was a completely new design with no circuitr … Wikipedia